ICS843071I datasheet(9/15 Pages) ICST

9 / 15 page

843071AGI

www.icst.com/products/hiperclocks.html

REV. A JANUARY 11, 2006

Integrated

Circuit

Systems, Inc.

ICS843071I

FEMTOCLOCKS™CRYSTAL-TO- LVPECL

CLOCK GENERATOR

TERMINATION FOR 3.3V LVPECL OUTPUT

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

FIGURE 3B. LVPECL OUTPUT TERMINATION

FIGURE 3A. LVPECL OUTPUT TERMINATION

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion. Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

ICS843071I Datasheet(PDF) 9 Page - Integrated Circuit Systems