2

7538AS

–CAN–09/05

AT90CAN32/64

2.

Description

2.1

Comparison Between AT90CAN32/64 and AT90CAN128

AT90CAN32/64 is hardware and software compatible with AT90CAN128, the only difference is

the memory size.

2.2

Part Desription

The AT90CAN32/64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RIS C architecture. By executing pow erful instructions in a single clock cycle, the

AT90CAN32/64 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The AT90CAN32/64 provides the following features: 32K/64K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 1K/2K bytes EEPROM, 2K/4K bytes SRAM, 53 gen-

eral purpose I/O lines, 32 general purpose working registers, a CAN controller, Real Time

Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte

oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differential input stage

with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial

port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip

Debug system and programming and five software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware

Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-

tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops

the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise

during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low power

consumption.

The device is manufactured using Atmel

’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

Table 2-1.

Memory Size Summary

Device

Flash

EEPROM

RAM

AT90CAN32

32K Bytes

1K Byte

2K Bytes

AT90CAN64

64K Bytes

2K Bytes

4K Bytes

AT90CAN128

128K Bytes

4K Byte

4K Bytes