SST26VF080A-80ESLASHMF datasheet(6/72 Pages) MICROCHIP

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DS20006203C-page 6

SST26VF080A

4.1

Device Protection

SST26VF080A offers a software write protection

scheme that allows group protection of selected blocks

in memory array. The Write Protection Pin (WP#)

enables or disables the lock-down (BPL bit) of the

STATUS

addition,

the

Lock-Down

Protection Settings command also prevents any

changes to the block protection setting (BP0, BP1 and

BP2) during device operation. To avoid inadvertent

writes during power-up, the device is write-protected by

default after a Power-on Reset cycle.

4.1.1

GROUP BLOCK PROTECTION

The Block Protection bits (BP0, BP1, BP2, and BPL) in

the STATUS register provide write protection to the

memory array and the STATUS register. See Table 4-4

for the Block Protection description.

4.1.2

VOLATILE LOCK PROTECTION

To prevent changes to the Block Protection settings,

use the Lock-Down Protection Settings (LDPS)

command to enable Volatile Lock Protection. Once

Volatile Lock Protection is enabled, the Block

Protection settings cannot be changed. To avoid

inadvertent lock-down, the WREN command must be

executed prior to the LDPS command. To reset Volatile

Lock Protection, performing a hardware Reset or

power cycle on the device is required. The Volatile Lock

Protection status may be read from the Configuration

4.2

Hardware Write Protection

The hardware Write Protection pin (WP#) is used in

conjunction with the WPEN and IOC bits in the

Configuration register to enable the lock-down function

of the BPL bit (bit 7) in the STATUS register and the

Configuration register. The WP# pin function only

works in SPI Single-Bit and Dual-Bit Read mode when

the IOC bit in the Configuration register is set to ‘0’. The

WP# pin function is disabled when the WPEN bit in the

Configuration register is ‘0’. This allows installation of

the device in a system with a grounded WP# pin while

still enabling write to the BP bits in the STATUS

The factory default setting at power-up of the WPEN bit

is ‘0’, disabling the Write-Protect function of the

WP# pin after power-up. WPEN is a nonvolatile bit;

once the bit is set to ‘1’, the Write-Protect function of

the WP# pin continues to be enabled after power-up.

The WP# pin only protects the BPL bit in STATUS

Therefore, if the WP# pin is set to low while an internal

write is in progress, it will have no effect on the write

command. The IOC bit takes priority over the WPEN bit

in the Configuration register. When the IOC bit is ‘1’, the

function of the WP# pin is disabled and the WPEN bit

serves no function. When WP# is driven low and IOC

bit = 0, the execution of the Write STATUS Register

(WRSR) instruction to change the BP bits in the STATUS

Table 4-1). When WP# is high, the lock-down function

of the BPL bit is disabled.

TABLE 4-1:

WRITE PROTECTION LOCK-DOWN STATES

VLP

WP#

IOC

WPEN

BPL

WRSR Instruction to Change BP0,

BP1, BP2, BP3 Bits in STATUS

WRSR Instruction to

Change Configuration

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Not Allowed

Allowed

Note 1: X = “Don’t care”.

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