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SST26VF080AT-80E/MF Datasheet(PDF) 13 Page - Microchip Technology |
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SST26VF080AT-80E/MF Datasheet(HTML) 13 Page - Microchip Technology |
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13 / 72 page ![]() 2019-2021 Microchip Technology Inc. DS20006203C-page 13 SST26VF080A 5.0 INSTRUCTIONS Instructions are used to read, write (erase and pro- gram), and configure the SST26VF080A. The com- plete list of the instructions is provided in Table 5-1. TABLE 5-1: DEVICE OPERATION INSTRUCTIONS Instruction Description Op Code Cycle(1) Mode Address Cycle(s)(2,3) Dummy Cycle(s)(3) Data Cycle(s)(3) Maximum Frequency (4) SPI SQI Configuration NOP No Operation 00H X X 0 0 0 104 MHz/80 MHz RSTEN Reset Enable 66H X X 0 0 0 RST Reset Memory 99H X X 0 0 0 EQIO Enable Quad I/O 38H X 0 0 0 RSTQIO Reset Quad I/O FFH X X 0 0 0 RDSR(5) Read STATUS Register 05H X 0 0 1 to ∞ X0 1 1 to ∞ WRSR Write STATUS Register 01H X X 0 0 1 to 2 RDCR Read Configuration Register 35H X 0 0 1 to ∞ X0 1 1 to ∞ Read READ Read Memory 03H X 3 0 1 to ∞ 40 MHz High-Speed Read Read Memory at Higher Speed 0BH X 3 1 1 to ∞ 104 MHz/80 MHz X3 3 1 to ∞ SDOR(6) SPI Dual Output Read 3BH X 3 1 1 to ∞ SDIOR (7,8) SPI Dual I/O Read BBH X 3 1 1 to ∞ 80 MHz SQOR (9) SPI Quad Output Read 6BH X 3 1 1 to ∞ 104 MHz/80 MHz SQIOR (10) SPI Quad I/O Read EBH X 3 3 1 to ∞ SB Set Burst Length C0H X X 0 0 1 RBSQI SQI nB Burst with Wrap 0CH X 3 3 n to ∞ RBSPI SPI nB Burst with Wrap ECH X 3 3 n to ∞ Identification JEDEC ID JEDEC® ID Read 9FH X 0 0 3 to ∞ 104 MHz/80 MHz Quad J-ID Quad I/O J-ID Read AFH X 0 1 3 to ∞ SFDP Serial Flash Discover- able Parameters 5AH X 3 1 1 to ∞ |
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