USB2641I datasheet(17/59 Pages) MICROCHIP

17 / 59 page

 2015-2021 Microchip Technology Inc.

DS00001948C-page 17

USB2640i/USB2641i

nRESET

RESET Input

The system uses this active low signal to reset the chip. The active low

pulse should be at least 1

s wide.

TEST

TEST Input

Tie this pin to ground for normal operation.

No Connects

No connect pins only apply to the USB2641I. No trace or signal should

be routed or attached to these pins.

DIGITAL / POWER / GROUND

CRFILT

VDD Core Regulator Filter Capacitor

This pin must have a 1.0

F (or greater)

20% (ESR <0.1 ) capacitor

to VSS.

VDD33

3.3 V Power and Voltage Regulator Inputs

Please refer to Section 9.0, "DC Parameters," on page 46 for more

information.

Pins 16 and 48 each require an external bypass capacitor of 4.7

F

minimum.

PLLFILT

PLL Regulator Filter Capacitor

This pin must have a 1.0

F (or greater)

20% (ESR <0.1 ) capacitor

to VSS.

VSS

ePad

The ground pad / ePad is the only VSS for the device and must be tied

to ground with multiple vias.

TABLE 6-1:

USB2640I/USB2641I PIN DESCRIPTIONS (CONTINUED)

Symbol

48-Pin

QFN

Buffer Type

(Table 6-2)

Description

USB2641I Datasheet(PDF) 17 Page - Microchip Technology

USB2641I Datasheet(HTML) 17 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL