PCIMX6DP7AYM2AB datasheet(48/168 Pages) NXP

48 / 168 page

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

Figure 7. Differential MLB Driver Transition Time Waveform

A 4-stage pipeline is used in the MLB 6-pin implementation to facilitate design, maximize throughput, and

allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from MLB PLL)

clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output delay of

Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data

clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.

MLB 6-pin pipeline diagram is shown in Figure 8.

Figure 8. MLB 6-Pin Pipeline Diagram

Table 33 shows the AC parameters for MLB I/O.

Table 33. I/O AC Parameters of MLB PHY

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Differential pulse skew1

1 t

SKD = | tPHLD –tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

tSKD

Rload = 50

between padP

and padN

——

0.1

Transition Low to High Time2

2 Measurement levels are 20-80% from output voltage.

tTLH

——

Transition High to Low Time

tTHL

——

MLB external clock Operating Frequency

fclk_ext

—

102.4

MHz

MLB PLL clock Operating Frequency

fclk_pll

—

307.2

MHz

padp

padn

VDIFF

0V (Differential)

VDIFF = {padp} - {padn}

tTLH

20%

80%

20%

80%

tTHL

VOH

VOL

PCIMX6DP7AYM2AB Datasheet(PDF) 48 Page - NXP Semiconductors

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