PCIMX6DP7AYM2AB datasheet(115/168 Pages) NXP

115 / 168 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018

NXP Semiconductors

115

4.12.13.6 Frame Transmission Mode (Synchronized Data Flow)

Figure 78. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)

4.12.13.7 Frame Transmission Mode (Pipelined Data Flow)

Figure 79. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)

4.12.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load

Table 70. DATA and FLAG Timing

Parameter

Description

1 Mbit/s 100 Mbit/s

tBit, nom

Nominal bit time

1000 ns

10 ns

tRise, min and tFall, min Minimum allowed rise and fall time

2 ns

tTxToRxSkew, maxfq

Maximum skew between transmitter and receiver package pins

50 ns

0.5 ns

tEageSepTx, min

Minimum allowed separation of signal transitions at transmitter package pins,

including all timing defects, for example, jitter and skew, inside the transmitter.

400 ns

4 ns

tEageSepRx, min

Minimum separation of signal transitions, measured at the receiver package pins,

including all timing defects, for example, jitter and skew, inside the receiver.

350 ns

3.5 ns

Complete N-bits Frame

DATA

FLAG

READY

Channel

Description

bits

Payload Data Bits

Frame

start bit

Complete N-bits Frame

DATA

FLAG

READY

Channel

Description

bits

Payload Data Bits

Frame

start bit

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