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PCIMX6DP7AYM2AB Datasheet(PDF) 125 Page - NXP Semiconductors |
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PCIMX6DP7AYM2AB Datasheet(HTML) 125 Page - NXP Semiconductors |
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125 / 168 page  Electrical Characteristics i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018 NXP Semiconductors 125 Figure 88. SPDIF_SR_CLK Timing Diagram Figure 89. SPDIF_ST_CLK Timing Diagram Table 80. SPDIF Timing Parameters Parameter Symbol Timing Parameter Range Unit Min Max SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns SPDIF_OUT output (Load = 50pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 24.2 31.3 ns SPDIF_OUT output (Load = 30pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.0 — ns SPDIF_SR_CLK low period srckpl 16.0 — ns Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns SPDIF_ST_CLK high period stclkph 16.0 — ns SPDIF_ST_CLK low period stclkpl 16.0 — ns SPDIF_SR_CLK (Output) VM VM srckp srckph srckpl SPDIF_ST_CLK (Input) VM VM stclkp stclkph stclkpl |
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