SCIMX6QP7AYM2AB datasheet(74/160 Pages) NXP

74 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

4.12.3

Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 45 shows the interface timing values. The number field in the table refers to timing

signals found in Figure 35 and Figure 36.

Table 45. Enhanced Serial Audio Interface (ESAI) Timing

Parameter1,2

Symbol

Expression2

Min

Max

Condition3 Unit

Clock cycle4

tSSICC

× Tc

30.0

—

i ck

Clock high period:

• For internal clock

• For external clock

—

× Tc − 9.0

× Tc

—

Clock low period:

• For internal clock

• For external clock

—

× Tc − 9.0

× Tc

—

ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high

—

19.0

7.0

x ck

i ck a

ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low

—

19.0

7.0

x ck

i ck a

ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

high5

—

19.0

9.0

x ck

i ck a

ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5

—

19.0

9.0

x ck

i ck a

ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high

—

19.0

6.0

x ck

i ck a

ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low

—

17.0

7.0

x ck

i ck a

Data in setup time before ESAI_RX_CLK (serial clock in

synchronous mode) falling edge

—

12.0

19.0

—

x ck

i ck

Data in hold time after ESAI_RX_CLK falling edge

—

3.5

9.0

—

x ck

i ck

ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK

falling edge5

—

2.0

19.0

—

x ck

i ck a

ESAI_RX_FS input (wl) high before ESAI_RX_CLK

falling edge

—

2.0

19.0

—

x ck

i ck a

ESAI_RX_FS input hold time after ESAI_RX_CLK falling

edge

—

2.5

8.5

—

x ck

i ck a

ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high

—

19.0

8.0

x ck

i ck

ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low

—

20.0

10.0

x ck

i ck

ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

high5

—

20.0

10.0

x ck

i ck

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