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SCIMX6QP7AYM2AB Datasheet(PDF) 118 Page - NXP Semiconductors |
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SCIMX6QP7AYM2AB Datasheet(HTML) 118 Page - NXP Semiconductors |
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118 / 160 page  i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 118 NXP Semiconductors Electrical Characteristics 4.12.18 SPDIF Timing Parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 71 and Figure 84 and Figure 85 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. SJ9 JTAG_TMS, JTAG_TDI data hold time 25 — ns SJ10 JTAG_TCK low to JTAG_TDO data valid — 44 ns SJ11 JTAG_TCK low to JTAG_TDO high impedance — 44 ns SJ12 JTAG_TRST_B assert time 100 — ns SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 40 — ns 1 T DC = target frequency of SJC 2 V M = mid-point voltage Table 71. SPDIF Timing Parameters Parameter Symbol Timing Parameter Range Unit Min Max SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns SPDIF_OUT output (Load = 50pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 24.2 31.3 ns SPDIF_OUT output (Load = 30pf) • Skew • Transition rising • Transition falling — — — — — — 1.5 13.6 18.0 ns Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns SPDIF_SR_CLK high period srckph 16.0 — ns SPDIF_SR_CLK low period srckpl 16.0 — ns Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns SPDIF_ST_CLK high period stclkph 16.0 — ns SPDIF_ST_CLK low period stclkpl 16.0 — ns Table 70. JTAG Timing (continued) ID Parameter1,2 All Frequencies Unit Min Max |
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