EZ80F92 datasheet(39/266 Pages) ZILOG

39 / 266 page

PS015309-1004

PRELIMINARY

eZ80F92/eZ80F93

Product Specification

Programmable Reload Counter/Timers (continued)

0087

TMR2_DR_L

Timer 2 Data Register—Low Byte

TMR2_RR_L

Timer 2 Reload Register—Low Byte

0088

TMR2_DR_H

Timer 2 Data Register—High Byte

TMR2_RR_H

Timer 2 Reload Register—High Byte

0089

TMR3_CTL

Timer 3 Control Register

R/W

008A

TMR3_DR_L

Timer 3 Data Register—Low Byte

TMR3_RR_L

Timer 3 Reload Register—Low Byte

008B

TMR3_DR_H

Timer 3 Data Register—High Byte

TMR3_RR_H

Timer 3 Reload Register—High Byte

008C

TMR4_CTL

Timer 4 Control Register

R/W

008D

TMR4_DR_L

Timer 4 Data Register—Low Byte

TMR4_RR_L

Timer 4 Reload Register—Low Byte

008E

TMR4_DR_H

Timer 4 Data Register—High Byte

TMR4_RR_H

Timer 4 Reload Register—High Byte

008F

TMR5_CTL

Timer 5 Control Register

R/W

0090

TMR5_DR_L

Timer 5 Data Register—Low Byte

TMR5_RR_L

Timer 5 Reload Register—Low Byte

0091

TMR5_DR_H

Timer 5 Data Register—High Byte

TMR5_RR_H

Timer 5 Reload Register—High Byte

0092

TMR_ISS

Timer Input Source Select Register

R/W

Table 4. Register Map (Continued)

Address

(hex)

Mnemonic

Name

Reset

(hex)

CPU

Access

Page

Notes:

1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-

out reset, the Watch-Dog Timer Control register is reset to 20h.

2. When the CPU reads this register, the current sampled value of the port is read.

3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked.

4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an

RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.

5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.

EZ80F92 Datasheet(PDF) 39 Page - Zilog, Inc.

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