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LTC4162EUFD-FSTM#PBF Datasheet(PDF) 5 Page - Analog Devices |
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LTC4162EUFD-FSTM#PBF Datasheet(HTML) 5 Page - Analog Devices |
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5 / 52 page ![]() 5 LTC4162-F Rev A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fOSC Switching Frequency RT = 63.4k l 1.4 1.5 1.6 MHz DMAX Maximum Duty Cycle 99.5 % RSWITCH Primary Switch On-Resistance 90 mΩ RRECT Rectifier Switch On-Resistance 90 mΩ IPEAK Peak Inductor Current Limit Note 3 45mV/RSNSB A System Controls VIN_UVLO VIN Charger Enable Input Undervoltage Lockout Rising Threshold Hysteresis 4.2 4.4 0.2 4.6 V V VIN_DUVLO VIN to BATSENS+ Charger Enable Differential Undervoltage Lockout Rising Threshold Hysteresis 100 150 170 200 mV mV VIN_OVLO VIN Charger Disable Overvoltage Lockout Rising Threshold Hysteresis 37.6 38.6 1.4 40 V V VINTVCC_UVLO INTVCC Telemetry Enable Undervoltage Lockout Rising Threshold Hysteresis 2.75 2.85 0.12 2.95 V V Telemetry A/D Measurement Subsystem IBAT (VCSP – VCSN) Resolution Offset Error Span Error IBAT = (VCSP – VCSN)/RSNSB 0.32mV < VCSP – VCSN < 32mV –0.15 –1 1.466 0.15 1 µV /LSB mV %rdng IIN (VCLP – VCLN) Resolution Offset Error Span Error IIN = (VCLP – VCLN)/RSNSI 0.32mV < VCLP – VCLN < 32mV –0.15 –1 1.466 0.15 1 µV/LSB mV %rdng VIN Resolution Offset Error Span Error 3V < VIN < 35V –25 –1 1.649 25 1 mV/LSB mV %rdng VBATSENS+ (Per cell_count) Resolution Offset Error Span Error 2V < VBATSENS+ < 3.8V –10 –1 192.4 10 1 µV/LSB mV %rdng VOUT Resolution Offset Error Span Error 3V < VOUT < 35V –25 –1 1.653 25 1 mV/LSB mV %rdng VNTC/VNTCBIAS Resolution Offset Error Span Error 0 < VNTC/VNTCBIAS < 1 –1 –1 45.833 1 1 µV/V/LSB mV/V %rdng T_die Resolution Offset 0.0215 –264.4 °C/LSB °C Serial Port, SDA, SCL, SMBALERT DVCC Logic Reference Level l 1.8 5.5 V IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA ADDRESS I2C Address 0b1101000[R/W] VIHI2C Input High Threshold 70 % DVCC VILI2C Input Low Threshold 30 % DVCC VOLI2C Digital Output Low (SDA/SMBALERT) ISDA/SMBALERT = 3mA 400 mV FSCL SCL Clock Frequency 400 kHz |
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