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SH7041A Datasheet(PDF) 226 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 226 Page - Renesas Technology Corp

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188
10.3.3
CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the
RD signal or WRx signal assert period
beyond the length of the
CSn signal assert period by setting the SW3–SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 10.6. Th and Tf
cycles are added respectively before and after the ordinary cycle. Only
CSn is asserted in these
cycles;
RD and WRx signals are not. Further, data is extended up to the T
f cycle, which is
effective for gate arrays and the like, which have slower write operations.
Th
T1
CK
Read
Write
Address
CSn
RD
Data
WRx
Data
T2
Tf
DACK
Figure 10.6
CS Assert Period Extension Function



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