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AS5047D Datasheet(PDF) 13 Page - ams AG |
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AS5047D Datasheet(HTML) 13 Page - ams AG |
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13 / 40 page ![]() ams Datasheet Page 13 [v1-07] 2016-Apr-27 Document Feedback AS5047D − Detailed Description Figure 15: SPI Read Figure 16: SPI Write Data Frame Figure 16 shows the structure of the Write Data Frame. The parity bit PARD must be calculated from the lower 15 bit of write data frame. In a SPI write transaction, the write command frame is followed by a write data frame at MOSI. The write data frame consists of the new register content, which was addressed is in the previous command frame. During data transmission on MOSI, the current register content is send on MISO. At the next command on MOSI the updated content of the register is transmitted on MISO, as shown in Figure 17. Bit Name Description 15 PARD Parity bit (even) 14 0 Always low 13:0 DATA Data Z Z ^ Z d d Z d DK^/ D/^K |
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