UCS2113 datasheet(42/62 Pages) MICROCHIP

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UCS2113

DS20005680B-page 42

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GENERAL CONFIGURATION 2 REGISTER (ADDRESS 12H)

R/W-0

U-0

R/W-0

U-1

U-0

ALERT2_MASK

—

DSCHG2

PWR_EN2S

—

EN_VBUS_DISCHG

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

C = Clear on

Read

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is

unknown

bit 7

ALERT2_MASK: Mask errors for all interrupts in Register 8-4 except OV_LIM2 and TSD.

1 = The ALERT#2 pin will only assert if a OV_LIM2 or TSD is detected

0 = The ALERT#2 pin will be asserted if an error condition or indicator event is detected

bit 6

Unimplemented

bit 5

DSCHG2: Forces the VBUS2 to be reset and discharged when the UCS2113 is in the Active state and

the EN_VBUS_DISCHG bit is logic '1'. Writing this bit to a logic '1' will cause the port power switch

to be opened and the discharge circuitry to activate to discharge VBUS. Actual discharge time is

controlled by DISCHG_TIME<1:0>. This bit must be cleared by the SMBus host after the forced VBUS

discharge.

1 =VBUS2 discharge initiated

0 = Port 2 not in discharge

bit 4

PWR_EN2S: Power Enable Port 2 override - This bit is OR’ed with the PWR_EN2 pin. Thus, if the

polarity is set to active-high, either the PWR_EN2 pin or this bit must be ‘1’ to enable the port power

switch.

bit 3

Unimplemented

bit 2

EN_VBUS_DISCHG: Enables VBUS discharge circuitry.

If it is '0', it completely disables all the automatic VBUS discharges from happening and allows only

manual VBUS discharges (the SMBus host must set and clear DISCHG_LOAD1 and DISCHG_-

LOAD2 bits from the Current Limit Behavior Registers 23h and 24h). Setting DSCHG1 and DSCHG2

bits from the General Configuration 1 and 2 registers 11h and 12h does not have any effect in this

case (Note 1).

If it is '1', the VBUS is discharged automatically as described in Section 6.4, VBUS Discharge. The

VBUS can be discharged manually by the SMBus host only by setting DSCHG1 and DSCHG2 bits

from the General Configuration 1 and 2 Registers 11h and 12h. Setting DISCHG_LOAD1 and

DISCHG_LOAD2 bits from the Current Limit Behavior Registers 23h and 24h doesn't have any effect

in this case.

bit 1-0

Unimplemented

Note 1: When the automatic VBUS discharges are disabled (EN_VBUS_DISCHG is '0'), the UCS2113 will not

check that the VBUS voltage is below the VTEST level after the manual VBUS discharges.

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