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CDCVF2509A

SCAS765A – APRIL 2004 – REVISED JULY 2004

Unlike many products containing PLLs, the CDCVF2509A does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2509A requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application of a

fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals.

The CDCVF2509A is characterized for operation from 0

°C to 85°C.

For application information, see application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking

(SSC) (SCAA039).

FUNCTION TABLE

Inputs

Outputs

PLL

AVDD

1G/2G

CLK

1Y/2Y

FBOUT

GND

H

L

L

L

Bypassed / Off

GND

H

H

H

H

Bypassed / Off

GND

L

L

L

L

Bypassed / Off

GND

L

H

L

H

Bypassed / Off

GND

L

Toggling

L

Toggling in phase to CLK

Bypassed / Off

3.3 V (nom)

L

H

L

L

On

3.3 V (nom)

L

Toggling

L

Toggling in phase to CLK

On

3.3 V (nom)

H

L

L

L

On

3.3 V (nom)

H

H

H

H

On

3.3 V (nom)

H

Toggling

Toggling in phase to CLK

Toggling in phase to CLK

On

3.3 V (nom)

X

< 1 MHz

L

L

Off

2