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8.3.4 I2C Bus Overview

The OPT3004 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are

essentially compatible with one another. The I2C interface is used throughout this document as the primary

example with the SMBus protocol specified only when a difference between the two protocols is discussed.

The OPT3004 is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional

data pin. The bus must be controlled by a controller device that generates the serial clock (SCL), controls the

bus access, and generates start and stop conditions. To address a specific device, the controller initiates a start

condition by pulling the data signal line (SDA) from a high logic level to a low logic level while SCL is high. All

targets on the bus shift in the target address byte on the SCL rising edge, with the last bit indicating whether

a read or write operation is intended. During the ninth clock pulse, the target being addressed responds to the

controller by generating an acknowledge bit by pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as

a start or stop condition. When all data are transferred, the controller generates a stop condition, indicated by

pulling SDA from low to high while SCL is high. The OPT3004 includes a 28-ms timeout on the I2C interface to

prevent locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.

8.3.4.1 Serial Bus Address

To communicate with the OPT3004, the controller must first initiate an I2C start command. Then, the controller

must address target devices via a target address byte. The target address byte consists of seven address bits

and a direction bit that indicates whether the action is to be a read or write operation.

Four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL.

Table 8-1 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the

ADDR pin is sampled on every bus communication and must be driven or connected to the desired level before

any activity on the interface occurs.

Table 8-1. Possible I2C Addresses with Corresponding ADDR Configuration

DEVICE I2C ADDRESS

ADDR PIN

1000100

GND

1000101

VDD

1000110

SDA

1000111

SCL

8.3.4.2 Serial Interface

The OPT3004 operates as a target device on both the I2C bus and SMBus. Connections to the bus are made via

the SCL clock input line and the SDA open-drain I/O line. The OPT3004 supports the transmission protocol for

standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data bytes

are transmitted most-significant bits first.

The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects

of input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise

immunity.

OPT3004

SBOS929A – DECEMBER 2018 – REVISED DECEMBER 2021

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