PCF8545ATT datasheet(38/54 Pages) NXP

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PCA8576F

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Product data sheet

Rev. 3 — 3 December 2014

38 of 54

NXP Semiconductors

PCA8576F

Automotive 40 × 4 LCD driver

14. Application information

14.1 Cascaded operation

In large display configurations, up to 8 PCA8576Fs can be differentiated on the same

I2C-bus by using the 2-bit hardware subaddresses (A0 and A1) and the programmable

I2C-bus slave address (SA0).

PCA8576Fs connected in cascade are synchronized to allow the backplane signals from

only one device in the cascade to be shared. This arrangement is cost-effective in large

LCD applications since the backplane outputs of only one device need to be

through-plated to the backplane electrodes of the display. The other PCA8576F of the

cascade contribute additional segment outputs. The backplanes can either be connected

together to enhance the drive capability or some can be left open-circuit (such as the ones

from the slave in Figure 29) or just some of the master and some of the slave will be taken

to facilitate the layout of the display.

All PCA8576Fs connected in cascade are correctly synchronized by the automatically

generated SYNC signal. The only time that SYNC is likely to be needed is if

synchronization is lost accidentally, for example, by noise in adverse electrical

environments, or if the LCD multiplex drive mode is changed in an application using

several cascaded PCA8576Fs, as the drive mode cannot be changed on all of the

cascaded devices simultaneously. SYNC can be either an input or an output signal; a

SYNC output is implemented as an open-drain driver with an internal pull-up resistor.

The PCA8576F asserts SYNC at the start of its last active backplane signal and monitors

the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first

PCA8576F to assert SYNC. The timing relationship between the backplane waveforms

and the SYNC signal for each LCD drive mode is shown in Figure 30.

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 23.

Table 22.

Addressing cascaded PCA8576F

Cluster

Bit SA0

Pin A1

Pin A0

Device

000

011

102

113

004

015

106

117

Table 23.

SYNC contact resistance

Number of devices

Maximum contact resistance

26 k



3 to 5

2.2 k



6 to 8

1.2 k



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