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STM32469VG Datasheet(PDF) 187 Page - STMicroelectronics |
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STM32469VG Datasheet(HTML) 187 Page - STMicroelectronics |
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187 / 220 page ![]() DS11189 Rev 7 187/220 STM32F469xx Electrical characteristics 191 Figure 75. DCMI timing diagram 5.3.32 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 109 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: LCD_CLK polarity: high LCD_DE polarity: low LCD_VSYNC and LCD_HSYNC polarity: high Pixel formats: 24 bits Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load CL = 30 pF Measurement points are done at CMOS levels: 0.5 VDD Table 108. DCMI characteristics(1) 1. 1.Guaranteed based on test during characterization. Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK -0.4 - DCMI_PIXCLK Pixel clock input - 54 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 4 - ns th(DATA) Data input hold time 1 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 3.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 0 - MS32414V2 DCMI_PIXCLK tsu(VSYNC) tsu(HSYNC) DCMI_HSYNC DCMI_VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) |
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