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STM32469VG Datasheet(PDF) 188 Page - STMicroelectronics |
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STM32469VG Datasheet(HTML) 188 Page - STMicroelectronics |
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188 / 220 page ![]() Electrical characteristics STM32F469xx 188/220 DS11189 Rev 7 Figure 76. LCD-TFT horizontal timing diagram Table 109. LTDC characteristics(1) 1. Based on test during characterization. Symbol Parameter Min Max Unit fCLK LTDC clock output frequency - 83 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH) tw(CLKL) Clock high time, low time tw(CLK) / 2 - 0.5 tw(CLK) / 2 + 0.5 ns tv(DATA) Data output valid time - 1.5 th(DATA) Data output hold time 0 - tv(HSYNC) HSYNC/VSYNC/DE output valid time - 0.5 tv(VSYNC) tv(DE) th(HSYNC) HSYNC/VSYNC/DE output hold time 0 - th(VSYNC) th(DE) MS32749V1 LCD_CLK tv(HSYNC) LCD_HSYNC LCD_DE LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] tCLK LCD_VSYNC tv(HSYNC) tv(DE) th(DE) Pixel 1 Pixel 2 tv(DATA) th(DATA) Pixel N HSYNC width Horizontal back porch Active width Horizontal back porch One line |
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