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STM32WB55CC Datasheet(PDF) 39 Page - STMicroelectronics |
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STM32WB55CC Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 193 page  DS11929 Rev 11 39/193 STM32WB55xx STM32WB35xx Functional overview 57 3.7.6 Reset mode To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.8 VBAT operation The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers) from an external battery, an external supercapacitor, or from VDD when no external battery nor an external supercapacitor are present. Three anti-tamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.9 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU1 resources and, consequently, reducing power supply consumption. In addition, these hardware connections result in fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and Sleep, Stop 0, Stop 1 and Stop 2 modes. Table 9. STM32WB55xx and STM32WB35xx CPU1 peripherals interconnect matrix Source Destination Action TIMx TIMx Timers synchronization or chaining Y Y Y Y - - ADC1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - COMPx TIM1 TIM2 Timer input channel, trigger, break from analog signals comparison YYY Y - - LPTIMERx Low-power timer triggered by analog signals comparison YYY YY Y(1) ADC1 TIM1 Timer triggered by analog watchdog Y Y Y Y - - |
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