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STM32WL55JC Datasheet(PDF) 19 Page - STMicroelectronics

Part # STM32WL55JC
Description  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  147 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL55JC Datasheet(HTML) 19 Page - STMicroelectronics

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DS13293 Rev 2
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STM32WL55/54xx
Functional overview
50
3.8
Global security controller (GTZC)
The GTZC includes the following sub-blocks:
•
TZSC: security controller
This sub-block defines the secure/privileged state of slave peripherals. It also controls
the unprivileged area size for the watermark memory peripheral controller (MPCWM).
•
TZIC: security illegal access controller
This sub-block gathers all illegal access events in the system and generates a secure
interrupt towards the secure CPU2 NVIC.
These sub-blocks are used to configure the system security and privilege such as:
•
on-chip Flash memory and RAM with programmable privileged protection on both
secure and non-secure memory areas
•
AHB and APB peripherals with programmable security and/or privileged access
3.9
Sub-GHz radio
3.9.1
Sub-GHz radio introduction
The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM
band. LoRa, (G)FSK/(G)MSK modulation in transmit and receive, and (D)BPSK in transmit
only, allow an optimal trade-off between range, data rate and power consumption. This
sub-GHz radio is compliant with the LoRaWAN® specification v1.0 and radio regulations
such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part 15, 24, 90, 101 and
the ARIB STD-T30, T-67, T-108.
The sub-GHz radio consists of:
•
an analog front-end transceiver, capable of outputting up to + 15 dBm maximum power
on its RFO_LP pin and up to + 22 dBm maximum power on RFO_HP pin
•
a digital modem bank providing the following modulation schemes:
–
LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)
5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)
–
FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s
–
(G)MSK Tx with BR from 0.1 to 10 Kbit/s
–
BPSK and DBPSK TX only with bitrate for 100 and 600 bit/s
•
a digital control including all data processing and sub-GHz radio configuration control
•
a high-speed clock generation
3.9.2
Sub-GHz radio general description
The sub-GHz radio provides an internal processing unit to handle communication with the
system CPU. Communication is handled by commands sent over the SPI interface, and a
set of interrupts is used to signal events. BUSY information signals operation activity and is
used to indicate when the sub-GHz radio commands cannot be received.



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