WF200D datasheet(21/38 Pages) SILABS

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4.8.2 SDIO Specification

Figure 4.2. SDIO Interface Timing Parameters

Table 4.13. SDIO Interface Timing Specifications

Symbol

Description

Min

Typ

Max

Unit

Conditions

tCLK_HS

Clock period in high speed

mode

19.23

CL ≤ 20pF

tCLK_DS

Clock period in default speed

mode

38.46

CL ≤ 20pF

tCLK_LO

Clock low time

CL≤ 20pF

tCLK_HI

Clock high time

CL≤ 20pF

CMD, DAT0~3 Inputs (with reference to SDIO_CLK)

tSU

Input Set time

CL≤ 20pF

tHD

Input Hold time

CL≤ 20pF

CMD, DAT0~3 Outputs (with reference to SDIO_CLK)

tODLY_CLKr,

tODLY_CLKf

Output delay time (relative to

rising and falling edge) for VDD

= 3.3V

VDDIO = 3.3V;

CL≤ 20pF

Output delay time (relative to

rising and falling edge) for VDD

= 1.8V

VDDIO = 1.8V;

CL≤ 20pF

tOH

Output Hold time

CL≤ 20pF

1. Output data can be latched either on rising edge (HS mode) or falling edge (DS mode) of CLK

2. All timing parameters valid for output load of up to 2 mA

WF200 Data Sheet: Wi-Fi® Network Co-Processor

Electrical Specifications

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