STM32WB50CG datasheet(118/119 Pages) STMICROELECTRONICS

118 / 119 page

Revision history

STM32WB50CG STM32WB30CE

118/119

DS13047 Rev 5

03-Jul-2020

Added STM32WB30CE device.

Updated Features, Section 2: Description, Section 3.3.4: Embedded

SRAM, Section 3.6.5: Typical RF application schematic, Section 6.3.10:

External clock source characteristics, Section 7.1: UFQFPN48 package

information and Section 8: Ordering information.

Updated Table 1: STM32WB50CG and STM32WB30CE device features

and peripheral counts, footnote of Table 3: RF pin list, Table 14:

STM32WB50CG and STM32WB30CE pin and ball definitions and its

footnotes, Table 15: Alternate functions, footnote 1 of Table 16: Voltage

characteristics, footnote 1 of Table 17: Current characteristics, Table 20:

General operating conditions, Table 22: RF transmitter BLE

characteristics (1 Mbps), Table 23: RF receiver BLE characteristics (1

Mbps), Table 26: RF receiver 802.15.4 characteristics, footnote 2 of

Table 48: HSE crystal requirements, Table 58: Flash memory

characteristics and Table 86: Package thermal characteristics.

Added footnotes to Table 19: Main performance at VDD = 3.3 V,

Table 24: RF BLE power consumption for VDD = 3.3 V, Table 27: RF

802.15.4 power consumption for VDD = 3.3 V and Table 76: VBAT

monitoring characteristics.

Updated Figure 6: Power supply overview, Figure 11: Power supply

scheme and Figure 22: ADC accuracy characteristics.

Added Figure 2: STM32WB30CExx block diagram and Figure 30:

STM32WB30CE UFQFPN48 marking example (package top view).

Added Table 49: HSE clock source characteristics.

Minor text edits across the whole document.

13-Apr-2021

Updated document title, Features, Section 1: Introduction, Section 2:

Description, Section 3.3.4: Embedded SRAM, Section 3.6: RF

subsystem, Section 3.6.2: BLE general description, Section 3.7.3: Power

supply supervisor, Section 3.14: Analog to digital converter (ADC),

Section 6.1.2: Typical values, Section 6.3.10: External clock source

characteristics, Section 7.1: UFQFPN48 package information and

Section 8: Ordering information.

Updated Table 1: STM32WB50CG and STM32WB30CE device features

and peripheral counts, Table 3: RF pin list, Table 5: Features over all

modes, Table 6: STM32WB50CG and STM32WB30CE modes overview,

Table 14: STM32WB50CG and STM32WB30CE pin and ball definitions,

Table 15: Alternate functions, Table 19: Main performance at VDD = 3.3

V, Table 29: Embedded reset and power control block characteristics,

Table 44: Peripheral current consumption, Table 49: HSE clock source

characteristics, footnote 2 of Table 51: Low-speed external user clock

characteristics and Table 76: VBAT monitoring characteristics.

Added Table 47: Wakeup time using USART.

Updated Figure 3: STM32WB50CG and STM32WB30CE RF front-end

block diagram, Figure 7: Clock tree and Figure 22: ADC accuracy

characteristics.

Table 87. Document revision history (continued)

Date

Revision

Changes

STM32WB50CG Datasheet(PDF) 118 Page - STMicroelectronics

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