AD9161BBCZRL datasheet(52/144 Pages) AD

52 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 52 of 144

Step 3: Data Streaming

In this phase, data is streamed from the transmitter block to the

receiver block.

Optionally, data can be scrambled. Scrambling does not start

until the very first octet following the ILAS.

The receiver block processes and monitors the data it receives

for errors, including the following:

•

Bad running disparity (8-bit/10-bit error)

•

Not in table (8-bit/10-bit error)

•

Unexpected control character

•

Bad ILAS

•

Interlane skew error (through character replacement)

If any of these errors exist, they are reported back to the

transmitter in one of the following ways (see the JESD204B

Error Monitoring section for details):

•

SYNCOUT± signal assertion: resynchronization

(SYNCOUT± signal pulled low) is requested at each error

for the last two errors. For the first three errors, an optional

resynchronization request can be asserted when the error

counter reaches a set error threshold.

•

For the first three errors, each multiframe with an error in

it causes a small pulse on SYNCOUT±.

•

Errors can optionally trigger an interrupt request (IRQ)

event, which can be sent to the transmitter.

For more information about the various test modes for

verifying the link integrity, see the JESD204B Test Modes

section.

Lane FIFO

The FIFOs in front of the crossbar switch and deframer synchro-

nize the samples sent on the high speed serial data interface

with the deframer clock by adjusting the phase of the incoming

data. The FIFO absorbs timing variations between the data

source and the deframer; this allows up to two PCLK cycles of

drift from the transmitter. The FIFO_STATUS_REG_0 register

and FIFO_STATUS_REG_1 register (Register 0x30C and

whether the FIFOs are full or empty.

Lane FIFO IRQ

An aggregate lane FIFO error bit is also available as an IRQ

event. Use Register 0x020, Bit 2 to enable the FIFO error bit,

and then use Register 0x024, Bit 2 to read back its status and

reset the IRQ signal. See the Interrupt Request Operation

section for more information.

Crossbar Switch

physical lanes (SERDINx±) to logical lanes used by the SERDES

deframers.

Table 21. Crossbar Registers

Address

Bits

Logical Lane

0x308

[2:0]

SRC_LANE0

0x308

[5:3]

SRC_LANE1

0x309

[2:0]

SRC_LANE2

0x309

[5:3]

SRC_LANE3

0x30A

[2:0]

SRC_LANE4

0x30A

[5:3]

SRC_LANE5

0x30B

[2:0]

SRC_LANE6

0x30B

[5:3]

SRC_LANE7

Write each SRC_LANEy with the number (x) of the desired

physical lane (SERDINx±) from which to obtain data. By

default, all logical lanes use the corresponding physical lane as

their data source. For example, by default, SRC_LANE0 = 0;

therefore, Logical Lane 0 obtains data from Physical Lane 0

(SERDIN0±). To use SERDIN4± as the source for Logical Lane 0

instead, the user must write SRC_LANE0 = 4.

Lane Inversion

can be used to ease routing of the SERDINx± signals. For each

Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.

Deframer

The AD9161/AD9162 consist of one quad-byte deframer

(QBD). The deframer accepts the 8-bit/10-bit encoded data

from the deserializer (via the crossbar switch), decodes it, and

descrambles it into JESD204B frames before passing it to the

transport layer to be converted to DAC samples. The deframer

processes four symbols (or octets) per processing clock (PCLK)

cycle.

The deframer uses the JESD204B parameters that the user has

programmed into the register map to identify how the data is

packed, and unpacks it. The JESD204B parameters are

described in detail in the Transport Layer section; many of the

parameters are also needed in the transport layer to convert

JESD204B frames into samples.

Descrambler

The AD9161/AD9162 provide an optional descrambler block

using a self synchronous descrambler with the following

polynomial: 1 + x14 + x15.

Enabling data scrambling reduces spectral peaks that are

produced when the same data octets repeat from frame to

frame. It also makes the spectrum data independent so that

possible frequency selective effects on the electrical interface do

not cause data dependent errors. Descrambling of the data is

enabled by setting the SCR bit (Register 0x453, Bit 7) to 1.

AD9161BBCZRL Datasheet(PDF) 52 Page - Analog Devices

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