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February 2020

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PI3DPX1202A

Document number: DS40115 Rev 3-3

PI3DPX1202A

Figures

Figure 2-1: Pre-channel length/insertion loss and EQ compensation............................................................ 3

Figure 3-1: PI3DPX1202A1 Package Pin-out ....................................................................................................... 8

Figure 3-2: PI3DPX1202A2 Package Pin-out ........................................................................................................ 9

Figure 4-1: Functional Block Diagram................................................................................................................... 12

Figure 4-2: Power up timing Sequence.................................................................................................................. 13

Figure 4-3: Internal power up timing sequence .................................................................................................. 13

Figure 4-4: Reset control from External Capacitor or GPO pin..................................................................... 14

Figure 4-5: Power up sequence flow chart ............................................................................................................ 15

Figure 4-6: Sink Test Request Transaction in Aux Link Training ................................................................. 21

Figure 5-1: DisplayPort Main Link Test Circuit.................................................................................................. 32

Figure 5-2: DisplayPort Main Link Intra-Skew Measurement........................................................................ 33

Figure 5-3: Rising and Falling Time Definition................................................................................................... 33

Figure 6-1: DP++ Source Application with combined Aux/DDC Channels.............................................. 34

Figure 6-2: DP Source Application with separate Aux/DDC Channels....................................................... 35

Figure 6-3: Decoupling Capacitor Placement Diagram.................................................................................... 37

Figure 6-4: Trace Width and Clearance of Micro-strip and Strip-line ......................................................... 38

Figure 6-5: 4-Layer PCB Stack-up Example......................................................................................................... 39

Figure 6-6: 6-Layer PCB Stack-up Example......................................................................................................... 39

Figure 6-7: Stitching Capacitor Placement ........................................................................................................... 40

Figure 6-8: Layout Guidance of Matched Differential Pair.............................................................................. 40

Figure 6-9: Layout Guidance of Bends................................................................................................................... 41

Figure 6-10: Layout Guidance of Shunt Component......................................................................................... 41

Figure 6-11: Layout Guidance of Series Component......................................................................................... 41

Figure 6-12: Layout Guidance of Stitching Via.................................................................................................... 42

Figure 6-13: DisplayPort Test Set-up...................................................................................................................... 43

Figure 6-14: DisplayPort 1.2 Compliance Test Report...................................................................................... 44

Figure 7-1: Package TQFN-48 (ZB) Mechanical Outline Dimension .......................................................... 45

Figure 7-2: TQFN-48 (ZB) Thermal Via Pad Area ........................................................................................... 46

Figure 7-3: General Part marketing information................................................................................................ 47

Figure 7-4: Tape & Reel label information............................................................................................................ 48

Figure 7-5: Tape leader and trailer pin 1 orientations ....................................................................................... 48

Figure 7-6: Standard embossed carrier tape dimensions.................................................................................. 49