Internal-Switch Boost Regulator with

Integrated 3-Channel Scan Driver for TFT LCDs

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13

Pin Description

PIN

NAME

FUNCTION

1

CKV

High-Voltage, Gate-Pulse Output. When enabled, CKV toggles between its high state (connected to

GON) and its low state (connected to GOFF) on each falling edge of the CPV input. Further, CKV is high

impedance whenever CPV and OE are both low or whenever CPV is low and OECON is high.

2

CKVCS

CKV Charge-Sharing Connection. CKVCS connects to CKV whenever CKV is high impedance to allow

connection to CKVB, sharing charge between the capacitive loads on these two outputs.

3

CKVBCS

CKVB Charge-Sharing Connection. CKVBCS connects to CKVB whenever CKVB is high impedance to

allow connection to CKV, sharing charge between the capacitive loads on these two outputs.

4

CKVB

High-Voltage, Gate-Pulse Output. CKVB is the inverse of CKV during active states and is high

impedance whenever CKV is high impedance.

5

STVP

High-Voltage, Start-Pulse Output. STVP is low (connected to GOFF) whenever STV is low and is high

(connected to GON) only when STV is high and CPV and OE are both low. When STV is high and either

CPV or OE is high, STVP is high impedance.

6

STV

Vertical Sync Input. The rising edge of STV begins a frame of data. The STV input is used to generate the

high-voltage STVP output.

7

OECON

Active-Low, Output-Enable Timing Input. OECON is driven by an RC-filtered version of the OE input signal. If

OE remains high long enough for the resistor to charge the capacitor up to the OECON threshold, the OE

signal is masked until OE goes low and the capacitor is discharged below the threshold through the resistor.

8

OE

Active-High, Gate-Pulse Output Enable. CKV and CKVB leave the high-impedance charge-sharing state

on the rising edge of OE.

9

CPV

Vertical Clock-Pulse Input. CPV controls the timing of the CKV and CKVB outputs that change state (by

first sharing charge) on its falling edge.

10

GND

Logic Ground

11

DISH

GOFF Discharge Input. Pulling DISH below ground activates an internal connection between GOFF and

GND, rapidly discharging the GOFF supply. Typically, DISH is capacitively connected to IN, so that

12

Supply Input. Logic supply input for the VCOM calibrator. Bypass to GND through a minimum 0.1μF

capacitor.

13

WPN

settings cannot be modified.

14

SCLS

alternate clock source.

15

SCL

16

SDA

17

WPP

Write-Protect Output. WPP is the inverse of WPN. It can be used to control active-high, write-protect

inputs on other devices.

18

SET

19

VL

3.3V On-Chip Regulator Output. This regulator powers internal analog circuitry for the step-up regulator,

op amp, and VCOM calibrator. External loads up to 10mA can be powered. Bypass VL to GND with a

0.22μF or greater ceramic capacitor.