LM5106MM datasheet(8/12 Pages) NSC

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Timing Diagrams

Operational Notes

The LM5106 is a single PWM input Gate Driver with Enable

that offers a programmable dead-time. The dead-time is set

with a resistor at the RDT pin and can be adjusted from

100ns to 600ns. The wide dead-time programming range

provides the flexibility to optimize drive signal timing for a

wide range of MOSFETS and applications.

The RDT pin is biased at 3V and current limited to 1 mA

maximum programming current. The time delay generator

will accommodate resistor values from 5k to 100k with a

dead-time time that is proportional to the RDT resistance.

Grounding the RDT pin programs the LM5106 to drive both

outputs with minimum dead-time.

STARTUP AND UVLO

Both top and bottom drivers include under-voltage lockout

(UVLO) protection circuitry which monitors the supply volt-

age (V

DD) and bootstrap capacitor voltage (HB – HS) inde-

pendently. The UVLO circuit inhibits each driver until suffi-

cient supply voltage is available to turn-on the external

MOSFETs, and the UVLO hysteresis prevents chattering

during supply voltage transitions. When the supply voltage is

applied to the V

DD pin of the LM5106, the top and bottom

gates are held low until V

DD exceeds the UVLO threshold,

typically about 6.9V. Any UVLO condition on the bootstrap

capacitor will disable only the high side output (HO).

LAYOUT CONSIDERATIONS

The optimum performance of high and low side gate drivers

cannot be achieved without taking due considerations during

circuit board layout. The following points are emphasized:

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FIGURE 2. LM5106 Input - Output Waveforms

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FIGURE 3. LM5106 Switching Time Definitions: t

LPLH,tLPHL,tHPLH,tHPHL

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FIGURE 4. LM5106 Enable: t

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FIGURE 5. LM5106 Dead-time: DT

LM5106MM Datasheet(PDF) 8 Page - National Semiconductor (TI)

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