9
Table-2: CPU Interface
Name
I/O
Description
CPUA0 ~
CPUA4
I
5 address lines for register
selection.
CPUD0 ~
CPUD7
I/O
8 data lines.
nCPUOE
I
Read enable signal, low active.
nCPUWE
I
Write enable signal, low active.
nCPUCS
I
Chip Select signal, low active.
CPUIRQ
O
Interrupt request signal.
UARTDI
I
UART input data line.
UARTDO
O
UART output data line.
Header
Address
Data
Checksum
Header
Address
Data
Checksum
Table-3: Other Interface
Name
I/O
Description
WCHDOG
O
Alive signal from ACD80800 to indicate
it is working properly.
nRESET
I
Hardware reset signal, low active.
VDD
-
3.3V power supply.
GND
-
Ground.
CPU Interface
The CPU interface provides a communication channel
between the CPU and the ACD80800. Basically, the
CPU sends command to the ACD80800 by writing into
associated registers, and retrieve result from ACD80800
by reading corresponding registers. The registers are
described in the section of “Register Description.” The
CPU interface signals are described by
table 2:
CPUAx is the address bus used to select the registers
of the ACD80800.
CPUDx is the data bus used to pass data between the
CPU and the registers of the ACD80800.
nCPUOE is used to control the timing of the read op-
eration.
nCPUWE is used to control the timing of the write op-
eration.
nCPUCS is used to make the ACD80800 active to the
nCPUOE or nCPUWE signals.
CPUIRQ is used to generate an interrupt request to the
CPU. For each source of the interrupt, refer to the de-
scription of the interrupt source register.
UARTDI is used by the control CPU to send command
into the ACD80800. The baud rate will be automatically
detected by the ACD80800. The result will be returned
through the UARTDO line with the detected baud rate.
The format of the command packet is shown as follows:
where:
•
Header is further defined as:
∗ b1:b0 - read or write, 01 for read,
11 for write
∗ b4:b2 - device number, 000 to 111
(0 to 7)
∗ b7:b5 - device type, 010 for ARL
•
Address - 8-bit value used to select the reg-
ister to access
•
Data - 32-bit value, only the LSB is used
for write operation, all 0 for read operation
•
Checksum - 8-bit value of XOR of all bytes
UARTDO is used to return the result of command ex-
ecution to the CPU. The format of the result packet is
shown as follows:
where:
•
Header is further defined as:
∗ b1:b0 - read or write, 01 for read,
11 for write
∗ b4:b2 - device number, 000 to 111
(0 to 7)
∗ b7:b5 - device type, 010 for ARL
•
Address - 8-bit value for address of the
selected register
•
Data - 32-bit value, only the LSB is used
for read operation, all 0 for write operation
•
Checksum - 8-bit value of XOR of all bytes
The ACD80800 will always check the CMD header to
see if both the device type and the device number
matches with its setting. If not, it ignores the command
and will not generate any response to this command.
Other Interface
(table 3)
WCHDOG signal is used to prevent the system from
hitting dead-lock by any abnormal event. Under normal
condition, the output signal from the WCHDOG pin will
not stay at low for longer than 10ms. If the state of
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