LIS3LV02DL datasheet(13/36 Pages) STMICROELECTRONICS

13 / 36 page

LIS3LV02DL

Application Hints

13/36

Application Hints

Figure 3.

LIS3LV02DL Electrical Connection

The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO

line. Power supply decoupling capacitors (100 nF ceramic, 10

µF Al) should be placed as near

as possible to the pin 13 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper behavior

of the IC (refer to Fig. 3). It is possible to remove Vdd mantaining Vdd_IO without blocking the

communication busses.

The functionality of the device and the measured acceleration data is selectable and accessible

through the I2C/SPI interface.When using the I2C, CS must be tied high while SDO must be left

floating. Refer to dedicated application note for further information on device usage.

4.1

Soldering Information

The LGA-16 package is lead free and green package qualified for soldering heat resistance

according to JEDEC J-STD-020C. Pin #1 indicator are physically connected to GND. Soldering

recommendations are available upon request.

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

Vdd_IO

10uF

Vdd

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

100nF

GND

LIS3LV02DL

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