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SMS45 Datasheet(PDF) 15 Page - Summit Microelectronics, Inc.

Part # SMS45
Description  Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
PDF  20 Pages
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Manufacturer  SUMMIT [Summit Microelectronics, Inc.]
Direct Link  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMS45 Datasheet(HTML) 15 Page - Summit Microelectronics, Inc.

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2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 11. Read and Write Operations
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover and the previously written data will be overwrit-
ten. As with the byte Write operation, all inputs are disabled
during the internal Write cycle. Refer to Figure 11 for the
address, Acknowledge, and data transfer sequence.
N
A
C
K
N
A
C
K
Typical Write Operation
(Standard memory device type)
S
T
A
R
T
A
C
K
B
A
2
B
A
1
A
8
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Master
SDA
Slave
0
1
10
A
C
K
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
S
T
A
R
T
Writing Configuration Registers
Master
SDA
Slave
01
10
Master
SDA
Slave
Device Type
Address
Bus
Address
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
R
/
W
A
C
K
S
T
A
R
T
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
Reading the Configuration Register
01
10
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
01
10
Up to 15
additional bytes
can be written
before issuing
the stop.
B
A
2
B
A
1
X
B
A
2
B
A
1
X
B
A
2
B
A
1
X
2047 Fig11
Typical Reading Operation
(Alternate memory device type)
Master
SDA
Slave
A
C
K
R
/
W
A
C
K
S
T
A
R
T
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
11
10
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
11
10
B
A
2
B
A
1
A
8
B
A
2
B
A
1
A
8
I2C PROGRAMMING INFORMATION (CONTINUED)



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