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SMS8198

2036 5.0 4/18/00

SMS8198

Tri Media

Processor

SDA

System Boot

Block

SCL

TRI_RESET#

VCR/Monitor

Audio

Local Reset

Audio

Camera

TRI_RESET#

WP

Peripheral

Peripheral

2036 ILL16.0

Figure 1. Typical Implementation of the SMS8198 and TriMedia Processor

The boot hardware operation begins with the assertion of

the reset signal TRI_RESET#. The TRI_RESET# output

TRI_RESET# is active the memory will be write protected.

In addition to the reset write protection feature, pin 7 can

be tied to a pull-up to disable the write function of the

memory. This effectively turns the memory array into an

inexpensive boot ROM.

After reset is de-asserted, only the system boot block is

allowed to operate. At this point the TriMedia processor

takes over and begins to download data from the memory

array into its system boot block. The data downloaded

contains configuration data to set up the TriMedia proces-

sor and to load special ID information into the PCI configu-

ration space register. The ID information is published in

the PCI configuration register to provide the 16 bit Sub-

system ID and Subsystem Vendor ID.

pulse width are programmable. Not only does this provide

maximum flexibility to the designer, but, as the processor

operating voltage levels migrate downwards, the

SMS8198 can be programmed to following this downward

trend. The values can be selected from the ordering

information table and the devices specified as standard

off-the-shelf items.