Pin Descriptions

Pin

Name

LLP Pin

Number

I/O, Type

Description

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+

SIA_0−

30

29

I, LVDS

Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,

CML, or LVPECL compatible.

SIA_1+

SIA_1−

19

20

I, LVDS

Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,

CML, or LVPECL compatible.

SIB_0+

SIB_0−

28

27

I, LVDS

Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,

CML, or LVPECL compatible.

SIB_1+

SIB_1−

21

22

I, LVDS

Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,

CML, or LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+

LI_0−

40

39

I, LVDS

Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

LI_1+

LI_1−

9

10

I, LVDS

Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+

SOA_0−

34

33

O, LVDS

Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(Notes 1, 3).

SOA_1+

SOA_1−

15

16

O, LVDS

Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(Notes 1, 3).

SOB_0+

SOB_0−

32

31

O, LVDS

Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(Notes 1, 3).

SOB_1+

SOB_1−

17

18

O, LVDS

Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(Notes 1, 3).

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+

LO_0−

42

41

O, LVDS

Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes

1, 3).

LO_1+

LO_1−

7

8

O, LVDS

Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes

1, 3).

DIGITAL CONTROL INTERFACE

MUX_S0

MUX_S1

38

11

I, LVTTL

Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed

through to the Line-side.

PREA_0

PREA_1

PREB_0

PREB_1

26

23

25

24

I, LVTTL

Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side

and B-side has a separate pin to control the pre-emphasis on or off.

PREL_0

PREL_1

44

5

I, LVTTL

Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and

B-side has a separate pin to control the pre-emphasis on or off.

ENA_0

ENA_1

ENB_0

ENB_1

36

13

35

14

I, LVTTL

Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side

and B-side has a separate enable pin.

ENL_0

ENL_1

45

4

I, LVTTL

Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a

separate enable pin.

www.national.com

2