PIC12F510-ISLASHLSQTP datasheet(59/114 Pages) MICROCHIP

59 / 114 page

Preliminary

DS41268B-page 57

PIC12F510/16F506

CONFIGURATION WORD – PIC16F506

—

IOSCFS MCLRE

WDTE

FOSC2

FOSC1

FOSC0

bit 11

bit 0

bit 11-7:

Unimplemented: Read as ‘1’

bit 6:

IOSCFS: Internal Oscillator Frequency Select bit

= 8 MHz INTOSC speed

= 4 MHz INTOSC speed

bit 5:

MCLRE: Master Clear Enable bit

= RB3/MCLR pin functions as MCLR

= RB3/MCLR pin functions as RB3, MCLR tied internally to VDD

bit 4:

CP: Code Protection bit

= Code protection off

= Code protection on

bit 3:

WDTE: Watchdog Timer Enable bit

= WDT enabled

= WDT disabled

bit 2-0:

FOSC2:FOSC0: Oscillator Selection bits

000

= LP oscillator and 18 ms DRT

001

= XT oscillator and 18 ms DRT

010

= HS oscillator and 18 ms DRT

011

= EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)

100

= INTOSC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)

101

= INTOSC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)

110

= EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)

111

= EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2)

Note 1: Refer to the “PIC16F506 Memory Programming Specification”, DS41258, to determine how to

access the Configuration Word.

2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal)

DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and

stability requirements for this mode of operation.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = bLANK

‘1’ = bit is set

‘0’ = bit is cleared

x = bit is unknown

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