CBTL05024

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 4 — 27 March 2014

11 of 21

NXP Semiconductors

CBTL05024

High performance MUX/deMUX switch for Thunderbolt applications

9.3 DP MUX channel characteristics

Table 13.

DDC - AUXIO channel of AUX MUX dynamic and static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ON-state resistance

-

35

50



input capacitance

-

0.2

-

pF

propagation delay

between DDC and AUXIO

-

70

-

ps

HIGH-level input leakage current

DDC_DAT and DDC_CLK pins;

--

1.5

A

LOW-level input leakage current

DDC_DAT and DDC_CLK pins;

--

1.5

A

Table 14.

Channel dynamic and static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

DDIL

differential insertion loss

DP-DPMLO path; channel is OFF

f= 2.7GHz

-

20

-

dB

f = 1.35 GHz

-

35

-

dB

f = 100 MHz

-

50

-

dB

DP-DPMLO path; channel is ON

f= 2.7GHz

-

1.2

-

dB

f = 1.35 GHz

-

1.1

-

dB

f = 100 MHz

-

0.8

-

dB



il(se)

single-ended insertion loss

LS-DPMLO path; channel is OFF;

f= 5MHz

-

60

-

dB

LS-DPMLO path; channel is ON;

f= 5MHz

-

1-

dB

DDRL

differential return loss

DP-DPMLO path

f= 2.7GHz

-

15

-

dB

f = 100 MHz

-

20

-

dB



rl(se)

single-ended return loss

LS-DPMLO path; f = 5 MHz

-

18

-

dB

DDNEXT

differential near-end crosstalk adjacent channels are ON

f= 5GHz

-

18

-

dB

f= 2.7GHz

-

25

-

dB

f = 100 MHz

-

60

-

dB

f= 1MHz

-

70

-

dB

ON-state resistance

-

9

12



-

16

22



initial ON-state resistance before

power supply negotiation done;

-35

50



3 dB bandwidth

differential; DP-DPMLO path

-

5.5

-

GHz

single-ended; LS-DPMLO path

-

1

-

GHz

propagation delay

between DP+/DP

 and

DPMLO+/DPMLO



-

100

-

ps

differential skew time

intra-pair

-

5

-

ps