MCP6V51-ESLASHMS datasheet(25/50 Pages) MICROCHIP

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DS20006136B-page 25

MCP6V51/2/4

4.3.6

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. These zero-drift op amps have a different

output impedance compared to standard linear

op amps, due to their unique topology.

When driving a capacitive load with these op amps, a

Series Resistor at the output (RISO in Figure 4-9)

improves the feedback loop’s phase margin (stability)

by making the output load resistive at higher frequen-

cies. The bandwidth will be generally lower than the

bandwidth with no capacitive load.

Figure 4-8 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

Load Capacitance (CL). The y-axis is the Resistance

(RISO).

GN is the circuit’s Noise Gain. For noninverting gains,

GN and the Signal Gain are equal. For inverting gains,

GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-8:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify the RISO value until the

response is reasonable. Bench evaluation is helpful.

4.3.7

STABILIZING OUTPUT LOADS

This family of zero-drift op amps has an output

impedance (Figure 2-28 and Figure 2-29) that has a

double zero when the gain is low. This can cause a

large phase shift in feedback networks that have low-

impedance near the part’s crossover frequency. This

phase shift can cause stability problems.

Figure 4-9 shows that the load on the output is

(RL + RISO)||(RF + RG), where RISO is before the load.

This load needs to be large enough to maintain

stability; it is recommended to design for a total load of

10 kΩ, or higher.

FIGURE 4-9:

Output Resistor, RISO,

Stabilizes Capacitive Loads.

4.3.8

GAIN PEAKING

Figure 4-10 shows an op amp circuit that represents

noninverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The CN and CG capacitances

represent the total capacitance at the input pins; they

include the op amp’s Common-Mode Input Capaci-

tance (CCM), board parasitic capacitance and any

capacitor placed in parallel. The CFP capacitance

represents the parasitic capacitance coupling between

the output and the noninverting input pins.

FIGURE 4-10:

Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

CG also reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing CG or RF||RG.

CN and RN form a low-pass filter that affects the signal

at VP. This filter has a single real pole at 1/(2πRNCN).

The largest value of RF that should be used depends

on the noise gain (see GN in Section 4.3.6

“Capacitive Loads”), CG and the open-loop gain’s

phase shift. An approximate limit for RF is shown in

Equation 4-4.

EQUATION 4-4:

100

1000

Normalized Load Capacitance; C

L/ GN (F)

1 V/V

10 V/V

100 V/V

DD = 45 V

L = 10 k

10p

100p

10n

100n

1μ

VOUT

MCP6V5X

–

RISO

VOUT

MCP6V5X

CFP

–

RF 10 k

3.5 pF

--------------- GN2

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