VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8169

OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

G52230-0, Rev 3.6

Page 13

01/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

35

NC

——

36

NC

——

37

NC

——

38

REF_FREQSEL

I

TTL

Reference clock input select

39

VCC

—

+3.3V

Positive power supply

40

VEE

—

GND

Negative power supply

41

FIFO_WARN

O

TTL

FIFO overflow warning

42

VEE

—

GND

Negative power supply

43

VCC

—

+3.3V

Positive power supply

44

RESET

I

TTL

Reset to align FIFO Write and Read pointers

45

NC

——

46

NC

——

47

NC

——

48

NC

——

49

NC

——

50

VCC

—

+3.3V

Positive power supply

51

VEE

—

GND

Negative power supply

52

CLK16O+

O

LVPECL

Low-speed clock output, true. A divide-by-16 version of the PLL clock.

53

CLK16O-

O

LVPECL

Low-speed clock output, complement. A divide-by-16 version of the

PLL clock.

54

VCC

—

+3.3V

Positive power supply

55

CLKI+

I

LVPECL

Low-speed clock input for latching low-speed data, true

56

CLKI-

I

LVPECL

Low-speed clock input for latching low-speed data, complement

57

VEE

—

GND

Negative power supply

58

D0-

I

LVPECL

Low-speed differential parallel data

59

D0+

I

LVPECL

Low-speed differential parallel data

60

VCC

—

+3.3V

Positive power supply

61

D1-

I

LVPECL

Low-speed differential parallel data

62

D1+

I

LVPECL

Low-speed differential parallel data

63

NC

——

64

VCC

—

+3.3V

Positive power supply

65

NC

——

66

VCC

—

+3.3V

Positive power supply

67

D2-

I

LVPECL

Low-speed differential parallel data

68

D2+

I

LVPECL

Low-speed differential parallel data

Pin #

Name

I/O

Level

Description