AMT49106 datasheet(23/74 Pages) ALLEGRO

23 / 74 page

Automotive Three-Phase MOSFET Driver

AMT49106

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Power Supplies

Two power supplies are required: a digital supply to power all

logic circuitry, and an analog supply to power other device func-

tions including the gate drive outputs.

The digital supply, VIO, should be connected to the VIO terminal.

This provides the supply voltage for the logic output terminals, the

reference for the logic input thresholds, and the input voltage to the

linear regulator that generates the supply for the core logic, VDD.

All internal logic is guaranteed to operate correctly to below the

regulator undervoltage levels, ensuring that the AMT49106 will

continue to operate safely until all logic is reset when a power-

on-reset state is present.

A 470 nF decoupling capacitor must be connected close to the

VIO and ground terminals. Additional external filtering should be

incorporated on these pins as required to mitigate noise propaga-

tion back into the system.

The analogue power supply, VBB, should be connected to the

VBB terminal through a reverse voltage protection circuit. A

100 nF ceramic decoupling capacitor must be connected close to

the VBB and ground terminals.

The output stage of each current sense amplifier is biased from

the voltage applied to the OOR terminal, VOOR. A capacitor may

be connected between the OOR terminal and ground to provide

filtering as required. VBB must be present to allow the current

sense amplifiers to operate. If VOOR is present and VBB drops

below the VBB undervoltage threshold, VBBUV, all amplifier

outputs are disabled and pulled to ground.

The VIO, VBB, and OOR terminals are each monitored by inter-

nal diagnostics to detect if the applied voltage is outside accept-

able limits. In the case of VIO and VOOR, these limits are set

to values appropriate for 5 V or 3.3 V operation according to the

state of the VLM and VLR bits in the Config 6 register.

Low Supply Voltage Operation

The AMT49106 will operate within specified parameters with

VBB from 4.5 to 50 V. For VBB less than 4.5 V, the outputs may

be disabled. As all logic circuitry is powered from the applied

VIO supply, the serial interface and core logic will operate even if

a VBB supply is not connected. In all cases, the AMT49106 will

operate safely between 0 and 50 V on the VBB supply, under all

supply switching conditions. This provides a very rugged solution

for use in the harsh automotive environment.

VREG Charge Pump Regulator

The gate drivers are powered by an internal voltage regulator

which generates a voltage, VREG, at the VREG terminal. It limits

the supply voltage to the drivers and therefore the maximum gate

voltage. At low supply voltage, the regulated supply is main-

tained by a charge pump boost converter.

This regulator uses a charge pump scheme with a switching fre-

quency of 62.5 kHz. It operates as a regulated doubler/tripler or a

step-down regulator depending on the input voltage on the VBB

terminal. Three external capacitors are required for the regulator to

operate: two pump capacitors and one storage capacitor. The pump

capacitors, CP1 and CP2 should have a nominal value of 2.2 µF and

be connected between the CP1 and CP2 terminals and between the

CP3 and CP4 terminals respectively. These devices should have a

rated working voltage of at least 50 V and a tolerance of ±20% or

better. The storage capacitor, CREG, is connected between the VREG

and GND terminals. The storage capacitor value will depend on the

size of the bootstrap capacitors and the total gate charge of the exter-

nal power MOSFETs. Further details on selecting the value of CREG

are provided in the Applications Notes section.

VCP Charge Pump Regulator

This regulator generates a voltage above the bridge supply, VBB.

It provides some of the switching current for the high-side drives,

the charge current for the bootstrap capacitors at high PWM duty

cycles, the bias current, and the gate drive current to hold the

high-side MOSFET in the on-state.

This regulator also uses a charge pump scheme with a switch-

ing frequency of 62.5 kHz. The voltage at the VREG terminal is

pumped to produce the required output. Two external capacitors are

required for the regulator to operate: one pump capacitor and one

storage capacitor. The pump capacitor, CP5, should have a nominal

value of 2.2 µF and be connected between the CP5 and CP6 ter-

minals. The storage capacitor, CVCP, should have a nominal value

of 2.2 µF and be connected between the VCP and VBB terminals.

Both the pump and storage capacitors should have a rated working

voltage of at least 25 V and a tolerance of ±20% or better.

One of four modes of operation may be selected according the value

of the CPM[1:0] bits in the Configuration 5 register. If CPM[1:0] is

set to 00b the regulator runs in auto mode. Average regulator current is

greater than 5 mA per phase until internal device logic detects that no

high-side gate drive has been commanded on for more than 200 μs and

then it drops back to a value of just over 200 μA per phase to reduce

device dissipation. Alternatively, if CPM[1:0] is set to 01b or 10b the

regulator will drive a fixed current of 200 μA or 5 mA respectively. If

CPM[1:0] is set to 11b, the regulator is turned off.

AMT49106 Datasheet(PDF) 23 Page - Allegro MicroSystems

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