 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ZMOD4450AI1R Datasheet(PDF) 14 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ZMOD4450AI1R Datasheet(HTML) 14 Page - Renesas Technology Corp |
|
|
14 / 22 page  ZMOD4450 Datasheet © 2021 Renesas Electronics Corporation 14 June 30, 2021 Figure 6. Bus Timing Table 9. Bus Timing Characteristics Symbol Parameter Standard Mode Fast Mode Units fSCL Maximum SCL clock frequency 100 400 kHz tHDSTA Minimum START condition hold time relative to SCL edge 4 µs tLOW Minimum SCL clock LOW width 4.7 µs tHIGH Minimum SCL clock HIGH width 4 µs tSUSTA Minimum START condition setup time relative to SCL edge 4.7 µs tHDDAT Minimum data hold time on SDA relative to SCL edge 0 µs tSUDAT Minimum data setup time on SDA relative to SCL edge 0.1 0.1 µs tSUSTO Minimum STOP condition setup time on SCL 4 µs tBUS Minimum bus free time between stop condition and start condition 4.7 µs SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSUSTO tBUS |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
