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TLV9162IDDFR Datasheet(PDF) 17 Page - Texas Instruments |
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TLV9162IDDFR Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 69 page ![]() 6.8 Typical Characteristics (continued) at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ (unless otherwise noted) Capacitive Load (pF) 0 80 160 240 320 400 480 560 0 10 20 30 40 50 60 70 D029 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 20-mVpp output step, G = –1 Figure 6-31. Small-Signal Overshoot vs Capacitive Load Capacitive Load (pF) 0 80 160 240 320 400 480 560 0 10 20 30 40 50 60 70 D030 RISO = 0:, Overshoot (+) RISO = 0:, Overshoot (-) RISO = 50:, Overshoot (+) RISO = 50:, Overshoot (-) 20-mVpp output step, G = +1 Figure 6-32. Small-Signal Overshoot vs Capacitive Load Capacitive Load (pF) 0 20 40 60 80 100 120 140 160 180 200 220 20 25 30 35 40 45 50 55 60 65 70 D004 G = +1 Figure 6-33. Phase Margin vs Capacitive Load Time (2 µs/div) -20 -10 0 10 20 D033 Input Output CL = 20 pF, G = 1, 20-mVpp step response Figure 6-34. Small-Signal Step Response Time (2 µs/div) -20 -10 0 10 20 D054 Input Output CL = 20 pF, G = –1, 20-mVpp step response Figure 6-35. Small-Signal Step Response Time (2 µs/div) -4 -3 -2 -1 0 1 2 3 4 D034 Input Output CL = 20 pF, G = 1, 5-Vpp step response Figure 6-36. Large-Signal Step Response www.ti.com TLV9161, TLV9162, TLV9164 SBOSA68B – NOVEMBER 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV9161 TLV9162 TLV9164 |
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