PIC16F87-ISLASHSS datasheet(94/214 Pages) MICROCHIP

94 / 214 page

PIC16F87/88

DS30487B-page 92

Preliminary

 2003 Microchip Technology Inc.

10.3

SSP I2C Mode Operation

The SSP module in I2C mode fully implements all slave

functions, except general call support, and provides

interrupts on START and STOP bits in hardware to

facilitate firmware implementations of the master func-

tions. The SSP module implements the standard mode

specifications, as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the

RB4/SCK/SCL pin, which is the clock (SCL), and the

RB1/SDI/SDA pin, which is the data (SDA). The user

must configure these pins as inputs or outputs through

the TRISB<4,1> bits.

The SSP module functions are enabled by setting SSP

Enable bit SSPEN (SSPCON<5>).

FIGURE 10-5:

SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has five registers for I2C operation:

• SSP Control register (SSPCON)

• SSP Status register (SSPSTAT)

• Serial Receive/Transmit Buffer register (SSPBUF)

• SSP Shift register (SSPSR) - Not directly

accessible

• SSP Address register (SSPADD)

The SSPCON register allows control of the I2C opera-

tion. Four mode selection bits (SSPCON<3:0>) allow

one of the following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Slave mode (7-bit address), with START and

STOP bit interrupts enabled to support firmware

Master mode

•I2C Slave mode (10-bit address), with START and

STOP bit interrupts enabled to support Firmware

Master mode

•I2C firmware controlled master operation with

START and STOP bit interrupts enabled, Slave is

IDLE

Selection of any I2C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISB bits. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I2C module.

Additional information on SSP I2C operation may be

found in the PICmicro® Mid-Range MCU Reference

Manual (DS33023).

10.3.1

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISB<4,1> set). The SSP module will

override the input state with the output data, when

required (slave-transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

Either or both of the following conditions will cause the

SSP module not to give this ACK pulse:

The buffer full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

The overflow bit, SSPOV (SSPCON<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set.

Table 10-2 shows what happens when a data transfer

byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow condi-

tion. Flag bit, BF, is cleared by reading the SSPBUF

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the SSP

module, are shown in timing parameter #100 and

parameter #101.

Read

Write

SSPSR Reg

Match Detect

SSPADD Reg

START and

STOP Bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, RESET

S, P Bits

(SSPSTAT Reg)

RB4/SCK/

RB1/

Shift

Clock

MSb

SDI/

LSb

SDA

SCL

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