Tr i p ath Technol ogy, I n c. - Techni cal I n for m ati on

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TLD4012 – JB/Rev. 2.0a/05.02

OVERVIEW

TLD4012 is a low-power, low-distortion ADSL line driver. This driver offers power consumption ranging

from 600mW to 650mW, and provides active, or synthetic, output impedance matching to reduce power

consumption. This driver supports an impedance synthesis factor of 2.55 (refer to Figure 1 in the

“Test/Applications Circuits” section of this document). The table below summarizes the total power

consumption of this device for FDM and overlapped transmissions. Power consumption is reduced by

using +/-14V supplies for VDD15/VSS15.

High supplies

VDD15/VSS15

Power consumption FDM

(non-overlapped)

(19.8dBm)

Power consumption

overlapped

(20.4dBm)

+/- 14.0 V

650 mW

710 mW

+/- 15.0 V

675 mW

740 mW

Power consumption values given above, and in the following specifications, are for total power consumed

from the supplies. This includes power dissipated in the device and power delivered to the load, where the

load includes both the line and the matching resistors. Power dissipation in the driver can be determined

by subtracting power delivered to the load (line and matching resistors) from the power consumption given

in the specifications. The power consumption provided above does not account for loading due to the

hybrid which will vary with application.

and a 5% supply tolerance. This is sufficient for full-power FDM signals with a PAR of 6.45. Note that

when using +/-14V supplies with a 5% tolerance the worst-case spurious free dynamic range in the

receiving band, and intermodulation distortion may be degraded slightly from the values given in the

specifications below. When using 14V nominal supplies the maximum degradation expected when the +/-

14V supplies are 5% low (minimum +/-13.3V) versus +/-15V supplies 5% low (minimum +/-14.25V) is less

than 4dB worse case.

All other minimum and maximum specifications in the tables that follow are valid from +/-13.3 to +/-15.75V

on VSS15/VDD15. This allows the use of +/-14V supplies with a 5% tolerance for VSS15/VDD15.

Lower PAR (peak-to-average ratio) values allow the high voltage supplies (VSS15 and VDD15) to be

reduced further, thus reducing power consumption. For example, for a 5.3 PAR VSS15/VDD15 can be

reduced to +/-12V. This will reduce power consumption to about 600mW for full-rate, 19.8dBm ADSL

FDM (non-overlapped) transmissions. Contact Tripath regarding use of the TLD4012 below +/-13.3V.

ratios to properly match the line are (see Figure 1 in “Test/Application” section below):

N = 1:1.4

100

Ω line impedance. The synthesis factor, k, is defined as the factor by which the line driver multiplies the

If your application can take advantage of higher synthesis factors, contact Tripath regarding options that

can reduce power consumption still further.