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HT95C20P Datasheet(PDF) 19 Page - Holtek Semiconductor Inc |
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HT95C20P Datasheet(HTML) 19 Page - Holtek Semiconductor Inc |
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19 / 51 page  HT95CXXX Rev. 1.50 19 May 26, 2005 By examining the processor status flags PDF and TO, the software program can distinguish between the dif- ferent ²chip resets². TO PDF Reset Condition 0 0 Power on reset uu External reset during Normal mode or Green mode 01 External reset during Sleep mode or Idle mode 1u WDT time-out during Normal mode or Green mode 11 WDT time-out during Sleep mode or Idle mode Note: ²u² means ²unchanged² The functional units chip reset status are shown below: Program Counter 000H Interrupt Disabled Prescaler Cleared WDT Cleared After a master reset, WDT begins counting. (If WDT function is enabled by mask option) Timer/Event Counter 0/1 Off Input/output Port Input mode Stack Pointer Points to the top of the stack W a r m R e s e t W D T C o l d R e s e t H A L T S Y S C L K S S T 1 0 - b i t R i p p l e C o u n t e r W D T T i m e - o u t E x t e r n a l R E S S y s t e m R e s e t Reset Configuration t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t Reset Timing Chart When the reset conditions occurred, some registers may be changed or unchanged. (HT95C400/40P) Register Addr. Reset Conditions Power On RES Pin RES Pin (Sleep/Idle) WDT WDT (Sleep/Idle) IAR0 00H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP0 01H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu IAR1 02H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 03H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP 04H ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu ACC 05H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 06H 0000H 0000H 0000H 0000H 0000H TBLP 07H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH 08H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 09H 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS 0AH --00 xxxx --uu uuuu --01 uuuu --1u uuuu --11 uuuu INTC0 0BH -000 0000 -000 0000 -000 0000 -000 0000 uuuu uuuu TMR0H 0CH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0L 0DH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 0EH 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- TMR1H 0FH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L 10H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 11H 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- |
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