7.6.1.2 SYNC Register (offset = 2h) [reset = 0000h]

Figure 7-5. SYNC Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

DAC-SYNC-

EN

W-0h

W-0h

W-0h

W-0h

W-0h

Table 7-4. SYNC Register Field Descriptions

Bit

Field

Type

Reset

Description

15-1

RESERVED

W

0h

These bits are reserved.

0

DAC-SYNC-EN

W

0h

When set to 1, the DAC output is set to update in response to an

LDAC trigger (synchronous mode).

When cleared to 0, the DAC output is set to update immediately

(asynchronous mode), default.

7.6.1.3 TRIGGER Register (offset = 5h) [reset = 0000h]

Figure 7-6. TRIGGER Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

LDAC

SOFT-RESET [3:0]

W-0h

W-0h

W-0h

Table 7-5. TRIGGER Register Field Descriptions

Bit

Field

Type

Reset

Description

15-5

RESERVED

W

0h

These bits are reserved.

4

LDAC

W

0h

Set this bit to 1 to synchronously load the DAC that is set to

synchronous mode in the SYNC register. This bit self-resets.

3-0

SOFT-RESET [3:0]

W

0h

When set to reserved code 1010, this bit resets the device to the

default state. This bit self-resets.

7.6.1.4 DAC Register (offset = 8h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when

RSTSEL is logic high]

Figure 7-7. DAC Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DAC-DATA [15:0]

W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high

Table 7-6. DAC Data Register Field Descriptions (8h)

Bit

Field

Type

Reset

Description

15-0

DAC-DATA [15:0]

W

0000h when

RSTSEL is

logic low

or

8000h when

RSTSEL is

logic high

Data are MSB aligned in straight binary format.

DAC82001

SBASAK3 – SEPTEMBER 2022

www.ti.com

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