STA8090WGR datasheet(18/32 Pages) STMICROELECTRONICS

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General description

STA8090WGR

18/32

DS12835 Rev 1

3.4.5

MTU

The 2 Multi Timer Units provide access to eight interrupt generating programmable 32-bit

Free-Running decrementing Counters (FRCs). The FRCs have their own clock input,

allowing the counters to run from a much slower clock than the system clock.

The FRC is the part of the timer that performs the counting. There are four instantiations of

the FRC block in each MTU, allowing eight counts to be performed in parallel. The 32-bit

counter in the FRC is split up into two 16-bit counters.

3.4.6

WDT

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog

clock is used to generate a regular interrupt (WDOGINT), depending on a programmed

value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt

remains unserviced for the entire programmed period. You can enable or disable the

watchdog unit as required.

Note:

Watchdog is stalled when the ARM processor is in Debug mode.

3.4.7

GPIO

The GPIO block provides Twelve (12) programmable inputs or outputs. Each input or output

can be controlled in two modes:



software mode through an APB bus interface



alternate mode, where GPIO becomes a peripheral input or output line

Any GPIO input can be independently enabled or disabled (masked) for interrupt

generation. User can select for each GPIO which edge (rising, falling, both) will trigger an

interrupt.

3.4.8

RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 32 Kbyte

SRAM and supplied with a dedicated voltage regulator.

The RTC provides a high resolution clock which can be used for GPS. It keeps the time

when the system is inactive and can be used to wake the system up when a programmed

alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the

32.768 kHz crystal and a secured time update.

RTC features



47-bit counter clocked by 32.768 kHz clock



32-bit for the integer part (seconds) and 15-bit for the fractional part



The integer part and the fractional part are readable independently



The counter, once enabled, can be stopped



Integer part load register (32-bit)



Fractional part load register (15-bit)



Load bit to transfer the content of the entire load register (integer+fractional part) to the

47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the

MCU that the RTC has been updated.

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