ARM940T datasheet(39/230 Pages) ETC1

39 / 230 page

Programmer’s Model

ARM DDI 0144B

2-21

In the case of nFIQ and nIRQ, the processor is woken up regardless of whether the

interrupts are enabled or disabled (that is, independent of the I and F bits in the

processor CPSR). The debug-related waking only occurs if DBGEN is HIGH, that is,

only when debug is enabled.

If the interrupts are enabled, the ARM core is guaranteed to take the interrupt before

executing the instruction after the wait-for-interrupt. If you use debug request to wake

up the system, the processor enters debug-state before executing any more instructions.

Drain write buffer

This CP15 operation causes instruction execution to be stalled until the write buffer is

emptied. This operation is useful in real-time applications where the processor has to be

sure that a write to a peripheral has completed before program execution continues. An

example is where a peripheral in a bufferable region is the source of an interrupt. When

the interrupt has been serviced, the request must be removed before interrupts can be

re-enabled. This can be ensured if a drain write buffer operation separates the store to

the peripheral and the enable interrupt functions.

The drain write buffer function is invoked by a write to CP15 register 7 using the

following ARM instruction:

MCR p15, 0, Rd, c7, c10, 4

This stalls the processor core, with CPnWAIT asserted until any outstanding accesses

in the write buffer have been completed, that is, until all data has been written to

memory.

2.3.11

You must not access (read or write) this register because it causes unpredictable

behavior.

2.3.12

These registers allow regions of the cache to be locked down. The opcode_2 field

determines if the instruction or data caches are programmed:

•

If the opcode_2 field = 0, the data lockdown bits are programmed. For example:

MCR/MRC p15, 0, Rd, c9, c0, 0

; data lockdown control

•

If the opcode_2 field = 1, the instruction lockdown bits are programmed. For

example:

MCR/MRC p15, 0, Rd, c9, c0, 1

; instruction lockdown control

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