IR1167ASPBF datasheet(7/15 Pages) IRF

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IR1167AS/BS

PRELIMINARY

GENERAL DESCRIPTION

The IR1167 Smart Rectifier IC can emulate the

operation of diode rectifier by properly driving a

Synchronous Rectifier (SR) MOSFET.

The direction of the rectified current is sensed by the

input comparator using the power MOSFET RDSon

as a shunt resistance and the GATE pin of the

MOSFET is driven accordingly.

Internal blanking logic is used to prevent spurious

transitions and guarantee operation in continuous

(CCM), discountinuous (DCM) and critical (CrCM)

conduction mode.

STATES OF OPERATION

UVLO/Sleep Mode

The IC remains in the UVLO condition until the voltage

on the VCC pin exceeds the VCC turn on threshold

voltage, V

CC ON.

During the time the IC remains in the UVLO state, the

gate drive circuit is inactive and the IC draws a

quiescent current of I

CC START.

The UVLO mode is

accessible from any other state of operation whenever

the IC supply voltage condition of VCC < V

CC UVLO

occurs.

The sleep mode is initiated by pulling the EN pin below

2.5V (typ). In this mode the IC is essentially shut down

and draws a very low quiescent supply current.

Normal Mode

The IC enters in normal operating mode once the

UVLO voltage has been exceeded. At this point the

gate driver is operating and the IC will draw a

maximum of ICC from the supply voltage source.

The modes of operation for a Flyback circuit differ

mainly for the turn-off phase of the SR switch, while

the turn-on phase of the secondary switch (which

correspond to the turn off of the primary side switch)

is identical.

Turn-on phase

When the conduction phase of the SR FET is initiated,

current will start flowing through its body diode,

generating a negative VDS voltage across it. The body

diode has generally a much higher voltage drop than

the one caused by the MOSFET on resistance and

therefore will trigger the turn-on threshold VTH2.

At that point the IR1167 will drive the gate of MOSFET

on which will in turn cause the conduction voltage VDS

to drop down. This drop is usually accompained by some

amount of ringing, that can trigger the input comparator

to turn off; hence, a Minimum On Time (MOT) blanking

period is used that will maintain the power MOSFET on

for a minimum amount of time.

The programmed MOT will limit also the minimum duty

VGate

VTH1

VTH2

VTH3

VDS

Input comparator thresholds

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