NAND04GR3B datasheet(15/59 Pages) STMICROELECTRONICS

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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B

BUS OPERATIONS

There are six standard bus operations that control

the memory. Each of these is described in this

section, see Table 5., Bus Operations, for a sum-

mary.

Typically, glitches of less than 5 ns on Chip En-

able, Write Enable and Read Enable are ignored

by the memory and do not affect bus operations.

Command Input

Command Input bus operations are used to give

commands to the memory. Commands are ac-

cepted when Chip Enable is Low, Command Latch

Enable is High, Address Latch Enable is Low and

Read Enable is High. They are latched on the ris-

ing edge of the Write Enable signal.

Only I/O0 to I/O7 are used to input commands.

See Figure 25. and Table 24. for details of the tim-

ings requirements.

Address Input

Address Input bus operations are used to input the

memory addresses. Four bus cycles are required

to input the addresses for the 512Mb and 1Gb de-

vices whereas five bus cycles are required for the

2Gb, 4Gb and 8Gb devices (refer to Table 6. and

Table 7., Address Insertion).

The addresses are accepted when Chip Enable is

Low, Address Latch Enable is High, Command

Latch Enable is Low and Read Enable is High.

They are latched on the rising edge of the Write

Enable signal. Only I/O0 to I/O7 are used to input

addresses.

See Figure 26. and Table 24. for details of the tim-

ings requirements.

Data Input

Data Input bus operations are used to input the

data to be programmed.

Data is accepted only when Chip Enable is Low,

Address Latch Enable is Low, Command Latch

Enable is Low and Read Enable is High. The data

is latched on the rising edge of the Write Enable

signal. The data is input sequentially using the

Write Enable signal.

See Figure 27. and Table 24. and Table 25. for de-

tails of the timings requirements.

Data Output

Data Output bus operations are used to read: the

data in the memory array, the Status Register, the

lock status, the Electronic Signature and the

Unique Identifier.

Data is output when Chip Enable is Low, Write En-

able is High, Address Latch Enable is Low, and

Command Latch Enable is Low.

The data is output sequentially using the Read En-

able signal.

See Figure 28. and Table 25. for details of the tim-

ings requirements.

Write Protect

Write Protect bus operations are used to protect

the memory against program or erase operations.

When the Write Protect signal is Low the device

will not accept program or erase operations and so

the contents of the memory array cannot be al-

tered. The Write Protect signal is not latched by

Write Enable to ensure protection even during

power-up.

Standby

When Chip Enable is High the memory enters

Standby mode, the device is deselected, outputs

are disabled and power consumption is reduced.

Table 5. Bus Operations

Note: 1. Only for x16 devices.

2. WP must be VIH when issuing a program or erase command.

Bus Operation

I/O0 - I/O7

I/O8 - I/O15(1)

Command Input

VIL

VIH

Rising

X(2)

Command

Address Input

VIL

VIH

VIL

VIH

Rising

Address

Data Input

VIL

VIH

Rising

VIH

Data Input

Data Output

VIL

Falling

VIH

Data Output

Write Protect

VIL

Standby

VIH

VIL/VDD

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