PCD8582D-2 datasheet(9/20 Pages) PHILIPS

9 / 20 page

December 1994

Philips Semiconductors

Product speciﬁcation

256 x 8-bit CMOS EEPROMS

with I2C-bus interface

PCX8582X-2 Family

WRITE OPERATIONS

Byte/word write

For a write operation the PCX8582X-2 requires a second

address field. This address field is a word address

providing access to the 256 words of memory. Upon

receipt of the word address the PCX8582X-2 responds

with an acknowledge and awaits the next eight bits of data,

again responding with an acknowledge. Word address is

automatically incremented. The master can now terminate

the transfer by generating a stop condition or transmit up

to six more bytes of data and then terminate by generating

a stop condition.

After this stop condition the ERASE/WRITE cycle starts

and the bus is free for another transmission. Its duration is

7 ms (typ.) per byte.

During the ERASE/WRITE cycle the slave receiver does

not send an acknowledge bit if addressed via the I2C-bus.

PAGE WRITE

The PCX8582X-2 is capable of an eight-byte page write

operation. It is initiated in the same manner as the byte

write operation. The master can transmit eight data bytes

within one transmission. After receipt of each byte the

PCX8582X-2 will respond with an acknowledge. The

typical ERASE/WRITE time in this mode is

× 7 ms = 63 ms.

After the receipt of each data byte the three low order bits

of the word address are internally incremented. The high

order five bits of the address remain unchanged. If the

master transmits more than eight bytes prior to generating

the stop condition, no acknowledge will be given on the

ninth (and following) data bytes and the whole

transmission will be ignored. As in the byte write operation,

all inputs are disabled until completion of the internal write

cycles.

PCD8582D-2 Datasheet(PDF) 9 Page - NXP Semiconductors