7.3.7 Power-Good Output

The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 95%

of the nominal voltage, and is driven low after the voltage falls below typically 90% of the nominal voltage. Table

7-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 10 mA. The

power-good output requires a pullup resistor connecting to any voltage rail less than 18 V. The PG signal can be

used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can

be left floating or connected to GND. PG has a deglitch time of typically 8 μs before going low.

Table 7-2. Power Good Pin Logic

DEVICE STATE

PG LOGIC STATUS

HIGH IMPEDANCE

LOW

Enabled (EN/SYNC = High)

VFB ≥ VPG

√

VFB < VPG after tPG

√

Shutdown (EN/SYNC = Low)

√

UVLO

0.7 V < VIN < VUVLO

√

Thermal Shutdown

TJ > TJSD

√

Power Supply Removal

VIN < 0.7 V

√

7.3.8 Noise Reduction and Soft-Start Capacitor (NR/SS)

A capacitor connected to this pin reduces the low frequency noise of the converter and sets the soft-start time.

The larger the capacitor, the lower the noise and the longer the start-up time of the converter. The module has

an internal 220-nF capacitor connected to the NR/SS pin. If no external capacitor is connected to the NR/SS

pin, the default start-up time is 2.35 ms, although longer start-up times and additional noise reduction can be

achieved with additional capacitance connected to the NR/SS pin. The maximum NR/SS cap is 3.3 µF for a

start-up time of 35 ms.During soft start with a light load, the device skips switching pulses as needed to not

discharge the output voltage. The device can start into a pre-biased output voltage.

The device achieves low noise by adding an R-C filter to the reference voltage, as shown in Functional Block

Diagram. During start-up, the NR/SS capacitor is charged with a constant current of 75 µA (typical) to 0.8 V.

Larger NR/SS capacitors provide for lower low frequency noise, as shown in Figure 6-29.

7.3.9 Current Limit and Short-Circuit Protection

The device is protected against short circuits and overcurrent. The switch current limit prevents the device from

high inductor current and from drawing excessive current from the input voltage rail. Excessive current can occur

with a shorted, saturated inductor or a heavy load, shorted output circuit condition. If the inductor current reaches

the threshold ISWpeak, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down

the inductor current. The high-side MOSFET is turned on again only when the low-side current is below the

low-side sourcing current limit ISWvalley.

Due to internal propagation delay, the actual current can exceed the static current limit, especially if the input

voltage is high and very small inductances are used. The dynamic current limit is calculated as follows:

(

)

L

peak typ

SWpeak

PD

V

I

I

t

L

§

·

u

¨

¸

©

¹

(1)

where

• ISWpeak is the static current limit, specified in Electrical Characteristics

• L is the inductance (2.2 μH for the TPSM8291x)

• VL is the voltage across the inductor (VIN – VOUT)

• tPD is the internal propagation delay, typically 50 ns

The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back

through the inductor to the input. This can happen during light load conditions or a pre-biased output condition.

TPSM82913

SLVSGJ4A – OCTOBER 2022 – REVISED DECEMBER 2022

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